1. Field of the Invention
The present invention relates to a semiconductor switch circuit used in a semiconductor integrated circuit. More particularly, the present invention relates to a semiconductor switch circuit that controls a conduction state and non-conduction state with low current consumption.
2. Description of the Related Art
The USB (Universal Serial Bus) is attracting attention as an interface standard for connecting a personal computer and peripheral devices. The USB transfers serial data using two signal lines, and a USB connector is connected to first and second signal lines for serial transmission of data, and a power supply IC for supplying power.
A semiconductor switch circuit is utilized as a semiconductor integrated circuit used in a USB connector and the like. A semiconductor switch circuit using MOS transistors is a typical analog signal switching means. The semiconductor switch circuit described in Patent Document 1 is a conventional semiconductor switch circuit.
FIG. 1 is a circuit diagram of the semiconductor switch circuit described in Patent Document 1, and the semiconductor switch circuit is an analog switch circuit used in a power supply IC.
In FIG. 1, semiconductor switch circuit 10 is configured with switch terminals 11 and 12, control terminals 13 and 14, a current mirror circuit Q20 configured with an N-type MOS transistor Q20a and N-type MOS transistor Q20b to which a source is grounded, a P-type MOS transistor Q21 for current supply that performs conduction control of current mirror circuit Q20, P-type MOS transistors Q22 and Q23 connected in series between switch terminals 11 and 12, and a resistance 24 connected between the gates and sources of P-type MOS transistors Q22 and Q23.
The operation of semiconductor switch circuit 10 configured as described above will now be explained.
P-type MOS transistor Q21 and current mirror circuit Q20 constitute a control system that controls the conduction state/non-conduction state of P-type MOS transistors Q22 and Q23 connected in series between switch terminals 11 and 12. When it is wished to establish conduction between switch terminals 11 and 12, a control signal applied to P-type MOS transistor Q21 gate control terminal 14 is driven low. As a result, P-type MOS transistor Q21 is turned on, and a drain current starts to flow, and this drain current is mirrored by current mirror circuit Q20 configured with N-type MOS transistors Q20a and Q20b. The drain potential of N-type MOS transistor Q20b tends to draw in current at the point of connection of P-type MOS transistors Q22 and Q23 via resistance 24, the gate potential of P-type MOS transistors Q22 and Q23 becomes 0 V. Consequently, P-type MOS transistors Q22 and Q23 enter a conduction state, a signal flows between switch terminals 11 and 12, and thereby switch-on is implemented.
On the other hand, when it is wished to establish a non-conduction state between switch terminals 11 and 12, the level of a control signal applied to control terminal 14 that is connected to the gate of P-type MOS transistor Q21 is made high. As a result, P-type MOS transistor Q21 is turned off, a current does not flow to current mirror circuit Q20 connected to the drain of P-type MOS transistor Q21, and current mirror circuit Q20 is turned off. As the gates of P-type MOS transistors Q22 and Q23 located between switch terminals 11 and 12 are both connected to the source of current mirror circuit Q20 via resistance 24, P-type MOS transistors Q22 and Q23 are connected in series in opposite directions. Therefore, a parasitic diode D11 of P-type MOS transistor Q22 and a parasitic diode D12 of P-type MOS transistor Q23 are connected in series in opposite directions, a non-conduction state is established between switch terminals 11 and 12, and switch-off is implemented.
If resistance 24 is not provided, upon switch-off, the gates of P-type MOS transistors Q22 and Q23 would not be connected simultaneously to the source of N-type MOS transistor Q20b, and the gate potentials of P-type MOS transistors Q22 and Q23 would float. That is to say, an unstable state would occur in which the P-type MOS transistors are turned on or turned off according to the gate potentials of P-type MOS transistors Q22 and Q23. By providing resistance 24 between the gates and sources of P-type MOS transistors Q22 and Q23, a state in which P-type MOS transistors Q22 and Q23 are connected in series in opposite directions—a state in which parasitic diodes D11 and D12 are connected in series in opposite directions—is realized, and a non-conduction state is reliably established upon switch-off.
However, with this kind of conventional semiconductor switch circuit, in order to establish conduction for P-type MOS transistors Q22 and Q23 formed between switch terminals 11 and 12, it is necessary to cause a current to flow from current mirror circuit Q20 to resistance 24 connected between the gates and sources of these P-type MOS transistors Q22 and Q23 and generate a potential difference in resistance 24. That is to say, a current is necessary to place semiconductor switch circuit 10 in the non-conduction state, and that current flows from a switch terminal, and therefore there is a problem that an excess leakage current flows from one of switch terminal 11 and switch terminal 12, which has the higher potential, and current consumption increases. Patent Document 1: Japanese Patent Application Laid-Open No. SHO 63-227215